This invention relates, in general, to power transistors, and more particularly to power transistors formed from a plurality of transistors coupled in parallel.
It is well known by those skilled in the art that many packaged high power transistors currently on the market comprise multiple power transistor die connected in parallel. The power transistor die connected in parallel may be unstable and oscillate when the packaged power transistor is used in a circuit application. This instability is due to variations in parasitic capacitance and inductance in the individual power transistor die and mutual coupling.
For example, packaged transistors such as a power MOSFET (metallic oxide semiconductor field effect transistor) or an IGBT (insulated gate bipolar transistor) are capable of withstanding over a thousand volts and conducting hundreds of amperes. A technique commonly employed to damp oscillations for these types of power transistors is to place a resistor between the gate of the power transistor and the gate of each individual transistor die which forms the power transistor. The resistor reduces the tendency for the power transistor to oscillate although ringing at the gate is common. An oscillating power device or severe ringing may be of dire consequence to many circuit designs.
It would be of great benefit if a technique could be developed which further decreased the tendency for paralleled power transistors to oscillate and dampens ringing.